1. Field of the Invention
The present invention relates to an analog-digital mixed master including a test circuit therein, and more specifically to an undelayer-fixed analog-digital mixed master including therein a test circuit for a Bi-CMOS analog/digital mixed LSI.
2. Description of Related Art
Recently, analog/digital mixed LSIs have been built to implement a large-scale analog circuit of high precision and a large-scale logic circuit on a single chip with development of Bi-CMOS (bipolar transistor/complementary metal-oxide-semiconductor transistor) process. Under this circumstance, a high speed operation, a low noise and a low power consumption have been demanded for an analog circuit section in the analog/digital mixed LSIs, and in addition, the analog circuit section is large-scale, because A/D converters, D/A converters and filters are implemented in the analog circuit section. 0n the other hand, the large-scale and the high speed are being rapidly advanced in the digital circuit section.
As a method for developing the analog/digital mixed LSIs, there has been conventionally widely adopted a process in which an analog circuit is designed by a manual means and a digital circuit is designed in a standard cell system, and then, both of the circuits are integrated on a single chip. This process has been advantageous since it is possible to design LSIs having many variations, but has been disadvantageous in that a long time period has been required for development, and therefore, a development expense has inevitably become high.
In order to compensate for the disadvantage of the conventional analog/digital mixed LSIs, there is an underlayer-fixed analog-digital mixed master system, in which an analog master composed of various analog circuit element such as transistors, resistors, capacitors, etc. which are located in the form of an array, and a digital gate array are previously implemented on a single chip. This can greatly reduce the development term and the development expense. On the other hand, with the shortening of the development term, it has become significant to analyze causes of malfunctions when the malfunctions have occurred in an operation of the LSI. In particular, because of complication of the circuits, a test method for discovering and eliminating defective chips has become more important.
In the prior art, for small-scale analog/digital mixed LSIs, the test has been performed without clearly separating the analog circuit section and the digital circuit section from each other. Namely, an analog signal and a digital signal are separately supplied to the analog circuit section and the digital circuit section, respectively, and a value of an output signal outputted from the analog circuit section and a pattern of signals outputted from the digital circuit section are derived from a manual calculation or a simulation.
However, in the conventional testing method for the analog/digital mixed LSIs, preparation of a test program needs a detailed thorough understanding of the whole of the analog circuit section and the digital circuit section, and in addition, the testing program itself is complicated.
In developing large-scale analog/digital mixed LSIs, it has been an ordinary practice that the design of the analog circuit section and the design of the digital circuit section are separately performed by different designers. Under this development structure, therefore, it has been difficult to prepare the testing program with the thorough understanding of the whole operation.
In addition, complication of the testing program makes it difficult to completely debug the testing program, and a long time period is necessary until the testing program becomes stable. Accordingly, the conventional test method as mentioned above for the analog/digital mixed LSIs is not convenient to the underlayer-fixed analog-digital mixed master in which the development term is the most preferential.
Furthermore, the conventional test method for the analog/digital mixed LSIs fails to easily determine which of the analog circuit section and the digital circuit section is defective, when malfunction occurs in the LSI.